1. Technical Field of the Invention
The present invention relates to the field of transistor driver circuits and in particular, to a low voltage differential signal driver for backplane applications.
2. Description of the Related Art
The constant need to transfer more information faster, accompanied by increases in data processing capability, necessitated an expansion to data transfer rates considerably higher than what was previously possible. As a consequence, a protocol referred to as 100 Base-T was developed for extending IEEE Standard 802.3 to accommodate data moving at an effective transfer rate of 100 Mbps through twisted-pair cables. Under the 100 Base-T protocol, certain control bits are incorporated into the data before it is placed on a twisted-pair cable. The result is that the data and control signals actually move through a twisted-pair cable at 125 Mbps.
One type of data transmission is differential data transmission in which the difference in voltage levels between two signal lines form the transmitted signal. Differential data transmission is commonly used for data transmission rates greater than 100 Mbps over long distances. Noise signals shift the ground level voltage and appear as common mode voltages. Thus, the deleterious effects of noise are substantially reduced.
To standardize such data transmission various standards have been promulgated. For example, one such standard is the recommended standard 422, RS422, which is defined by the Electronics Industry of America, EIA. This standard permits data rates up to 10 million baud over a twisted pair of signal lines. Driver circuits place signals on the lines. These drivers circuits must be capable of transmitting a minimum differential signal in the range of two to three volts on the twisted pair line which typically terminates in 100 ohms of resistance.
One problem with RS422 is that the twisted line pair is often used as a bus to which multiple driver circuits, sources of signals, are attached. In one type of conventional circuit, when multiple drivers are connected to a common bus, only one driver may transmit data at a time. The remaining drivers should be in a high impedance state so as to not load the bus. Since large positive and negative common mode signals may appear at the driver output terminals connected to a bus system, the maintenance of a high impedance over a wide common mode voltage range independent of whether the driver is powered or not, is desirable.
An example of a conventional low voltage differential signal (LVDS) driver circuit 100 is shown in FIG. 1. The difference in voltage between the output signals OUT+, OUT- on the output terminals 103, 105 form the pair of differential signals. A pair of differential signals means two signals whose current waveforms are out of phase with one another.
The LVDS driver circuit 100 includes a direct current (DC) constant current source I1 coupled to voltage supply VDD, four n-channel metal oxide semiconductor (NMOS) switches M11-M14, and a resistor R1 coupled between the common node COM and voltage supply VSS. The four transistor switches M11-M14 are controlled by input voltage signals VIN1, VIN2 and direct current through load resistor Rt as indicated by arrows A and B. The input voltage signals VIN1, VIN2 are typically rail-to-rail voltage swings.
The gates of NMOS switches M11 and M14 couple together to receive input voltage signal VIN1. Similarly, the gates of NMOS switches M12 and M13 couple together to receive input voltage signal VIN2.
Operation of the LVDS driver circuit 100 is explained as follows. Two of the four NMOS switches M11-M14 turn on at a time to steer current from current source I1 to generate a voltage across resistive load Rt. To steer current through resistive load Rt in the direction indicated by arrow A, input signal VIN2 goes high turning ON NMOS switches M12 and M13. When input signal VIN2 goes high, input signal VIN1 goes low to keep NMOS switches M11 and M14 OFF during the time NMOS switches M12 and M13 are ON. Conversely, to steer current through resistive load Rt in the direction indicated by arrow B, input signal VIN1 goes high and is applied to transistor switches M11 and M14 to make them conduct. Input signal VIN2 goes low to keep NMOS switches M12 and M13 OFF during this time. As a result, a full differential output voltage swing can be achieved.
Differential LVDS driver circuit 100 works well as long as the output voltage swing stays within the allowable common mode voltage range, usually a few volts. In general, LVDS driver circuit 100 can provide current to resistive load Rt only over some finite range of load resistance. The output voltage range over which the LVDS driver circuit 100 can function properly is known as its output compliance.
One drawback of conventional LVDS driver circuit 100 is the limited range in which to account for voltage output compliance. Typically, conventional LVDS driver circuit 100 is intended to supply a constant current from DC current source I1 to a fixed resistance of resistive load Rt. The problem often arises when LVDS driver circuit 100 connects to a backplane bus which terminates at multiple resistive loads Rt. When multiple resistive loads Rt are connected in parallel, the total resistance of resistive load Rt decreases. Since the high output voltage VOH is the voltage at the output of either output transistors M11 or M13 depending upon which switching transistor M11, M13 is conducting, this high output voltage VOH depends on the total resistance of resistive load Rt. Since the current from current source I1 is constant, when that resistance of resistive load Rt decreases, high output voltage VOH across the resistive load Rt decreases. The differential output voltage VOD is equal to high output voltage VOH less low output voltage VOL, as shown in the equation below, where low output voltage VOL is the voltage at the output of either transistor M11 or M14 depending upon which switching transistor M11, M14 is conducting. EQU VOD=VOH-VOL (1)
When the total resistance of resistive load Rt decreases such that the voltage across resistive load Rt falls below the minimum tolerance level of high output voltage VOH, the differential output voltage signal VOD will be too small and therefore difficult to read. On the other hand, if the resistance of the resistive load Rt increases such that the voltage across resistive load Rt exceeds the maximum tolerance level of high output voltage VOH, LVDS driver circuit 100 can be pushed out of voltage compliance.
Another drawback of LVDS driver circuit 100 is an unbalanced output impedance. Ideally, LVDS driver circuit 100 should have zero output impedance. The DC current source I1 at the top of the LVDS driver circuit 100 has a high output impedance. In contrast, resistor R1, which typically is a small value resistor, at the bottom of the LVDS driver circuit 100 has a low impedance. This impedance mismatch causes rise and fall time mismatches for the LVDS driver circuit 100 which in turn causes power to be reflected on the bus creating undesirable noise, such as electromagnetic interference (EMI) on the common mode voltage.
Therefore, a need exists for a LVDS driver circuit that limits the output voltage drop across the resistive load and eliminates impedance mismatch.